very low power cmos sram 32k x 8 bit bs62lv256 r0201-bs62lv256 revision 2.7 oct. 2008 1 pb-free and green package materials are compliant to rohs ? features y wide v cc operation voltage : 2.4v ~ 5.5v y very low power consumption : v cc = 3.0v operation current : 25ma (max.) at 70ns 1ma (max.) at 1mhz standby current : 0.4/0.7ua(max.) at 70 o c/85 o c v cc = 5.0v operation current : 40ma (max.) at 55ns 2ma (max.) at 1mhz standby current : 4/5ua (max.) at 70 o c/85 o c y high speed access time : -55 55ns(max.) at v cc : 4.5~5.5v -70 70ns(max.) at v cc : 3.0~5.5v y automatic power down when chip is deselected y easy expansion with ce and oe options y three state outputs and ttl compatible y fully static operation y data retention supply voltage as low as 1.5v ? description the bs62lv256 is a high performance, very low power cmos static random access memory organized as 32,768 by 8 bits and operates form a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and ci rcuit techniques provide both high speed and low power features with maximum cmos standby current of 0.7ua/5ua at 3v/5v at 85 o c and maximum access time of 55/70ns. easy memory expansion is provided by an active low chip enable (ce), and active low output enable (oe) and three-state output drivers. the bs62lv256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the bs62lv256 is available in dice form, jedec standard 28 pin 330mil plastic sop, 600mil plastic dip, 8mmx13.4mm tsop (normal type). ? power consumption power dissipation standby (i ccsb1 , max) operating (i cc , max) v cc =5.0v v cc =3.0v product family operating temperature v cc =5.0v v cc =3.0v 1mhz 10mhz f max. 1mhz 10mhz f max. pkg type bs62lv256dc dice bs62lv256pc pdip-28 bs62lv256sc sop-28 bs62lv256tc commercial +0 o c to +70 o c 4.0ua 0.4ua 1.5ma 18ma 35ma 0.8ma 12ma 20ma tsop-28 bs62lv256pi pdip-28 bs62lv256si sop-28 bs62lv256ti industrial -40 o c to +85 o c 5.0ua 0.7ua 2ma 20ma 40ma 1ma 15ma 25ma tsop-28 ? pin configurations ? block diagram brilliance semiconductor, inc. reserves the right to change products and specifications without notice. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 bs62 l v 256pc bs62lv256pi bs62lv256sc bs62 l v 256si ? address input buffer row decoder memory array 512x512 column i/o write driver sense am p column decoder address input buffer a3 a2 a1 a0 a10 data input buffer control dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a5 a6 a7 a12 a14 a13 a8 a9 a11 8 8 8 8 6 64 512 512 9 a4 ce we oe v cc gnd data output buffer a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 bs62 l v 256tc bs62lv256ti 28 27 26 25 24 23 22 21 20 19 18 17 16 15
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 2 ? pin descriptions name function a0-a14 address input these 15 address inputs select one of the 32,768 x 8-bit in the ram ce chip enable input ce is active low. chip enable must be active when data read form or write to the device. if chip enable is not active, the dev ice is deselected and is in standby power mode. the dq pins will be in the high impedanc e state when the device is deselected. we write enable input the write enable input is active low and c ontrols read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, dat a will be present on the dq pins and they will be enabled. the dq pins will be in the high impendence state when oe is inactive. dq0-dq7 data input/output ports there 8 bi-directional ports are used to read data from or write data into the ram. v cc power supply gnd ground ? truth table mode ce we oe i/o operation v cc current not selected (power down) h x x high z i ccsb , i ccsb1 output disabled l h h high z i cc read l h l d out i cc write l l x d in i cc notes: h means v ih ; l means v il ; x means don?t care (must be v ih or v il state) ? absolute maximum ratings (1) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 (2) to 7.0 v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. ?2.0v in case of ac pulse width less than 30 ns. ? operating range rang ambient temperature v cc commercial 0 o c to + 70 o c 2.4v ~ 5.5v industrial -40 o c to + 85 o c 2.4v ~ 5.5v ? capacitance (1) (t a = 25 o c, f = 1.0mhz) symbol pamameter conditions max. units c in input capacitance v in = 0v 6 pf c io input/output capacitance v i/o = 0v 8 pf 1. this parameter is guaranteed and not 100% tested.
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 3 ? dc electrical characteristics (t a = -40 o c to +85 o c) parameter name parameter test conditions min. typ. (1) max. units v cc power supply 2.4 -- 5.5 v v il input low voltage -0.5 (2) -- 0.8 v v ih input high voltage 2.2 -- v cc +0.3 (3) v i il input leakage current v in = 0v to v cc -- -- 1 ua i lo output leakage current ce= v ih , or oe = v ih , v i/o = 0v to v cc -- -- 1 ua v ol output low voltage v cc = max, i ol = 0.5ma -- -- 0.4 v v oh output high voltage v cc = min, i oh = -0.5ma 2.4 -- -- v v cc =3.0v -- -- 25 i cc (5) operating power supply current ce = v il , i dq = 0ma, f = f max (4) v cc =5.0v -- -- 40 ma v cc =3.0v -- -- 1 i cc1 operating power supply current ce = v il , i dq = 0ma, f = 1mhz v cc =5.0v -- -- 2 ma v cc =3.0v -- -- 1.0 i ccsb standby current ? ttl ce = v ih , i dq = 0ma v cc =5.0v -- -- 2.0 ma v cc =3.0v -- 0.01 0.7 i ccsb1 (6) standby current ? cmos ce R v cc -0.2v, v in R v cc -0.2v or v in Q 0.2v v cc =5.0v -- 0.4 5.0 ua 1. typical characteristics are at t a =25 o c and not 100% tested. 2. undershoot: -1.0v in case of pulse width less than 20 ns. 3. overshoot: v cc +1.0v in case of pulse width less than 20 ns. 4. f max =1/t rc. 5. i cc (max.) is 20ma/35ma at v cc =3.0v/5.0v and t a =70 o c. 6. i ccsb1(max.) is 0.4ua/4.0ua at v cc =3.0v/5.0v and t a =70 o c. ? data retention characteristics (t a = -40 o c to +85 o c) symbol parameter test conditions min. typ. (1) max. units v dr v cc for data retention ce R v cc -0.2v, v in R v cc -0.2v or v in Q 0.2v 1.5 -- -- v i ccdr (3) data retention current ce R v cc -0.2v, v in R v cc -0.2v or v in Q 0.2v -- 0.01 0.4 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns 1. typical characteristics are at v cc =1.5v, t a =25 o c and not 100% tested. 2. t rc = read cycle time. 3. i ccrd(max.) is 0.3ua at t a =70 o c. ? low v cc data retention waveform (ce controlled) data retention mode v cc t cdr v cc t r v ih v ih ce R v cc - 0.2v v dr R 1.5v ce v cc
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 4 ? ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc t clz , t olz , t chz , t ohz , t whz c l = 5pf+1ttl output load others c l = 100pf+1ttl 1. including jig and scope capacitance. ? key to switching waveforms waveform inputs outputs must be steady must be steady may change from ?h? to ?l? will be change from ?h? to ?l? may change from ?l? to ?h? will be change from ?l? to ?h? don?t care any change permitted change : state unknow does not apply center line is high inpedance ?off? state ? ac electrical characteristics (t a = -40 o c to +85 o c) read cycle cycle time : 55ns (v cc = 4.5~5.5v) cycle time : 70ns (v cc = 3.0~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t rc read cycle time 55 -- -- 70 -- -- ns t av q x t aa address access time -- -- 55 -- -- 70 ns t e1lqv t acs chip select access time -- -- 55 -- -- 70 ns t glqv t oe output enable to output valid -- -- 25 -- -- 35 ns t e1lqx t clz chip select to output low z 10 -- -- 10 -- -- ns t glqx t olz output enable to output low z 10 -- -- 10 -- -- ns t e1hqz t chz chip select to output high z -- -- 30 -- -- 35 ns t ghqz t ohz output enable to output high z -- -- 25 -- -- 30 ns t av q x t oh data hold from address change 10 -- -- 10 -- -- ns c l (1) 1 ttl output all input pulses 90% v cc gnd rise time : 1v/ns fall time : 1v/ns 90%
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 5 ? switching waveforms (read cycle) read cycle 1 (1,2,4) read cycle 2 (1,3,4) read cycle 3 (1, 4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. t clz (5) d out ce t a cs t chz (5) t oh t rc t oe d out ce oe address t clz (5) t a cs t chz (1 , 5) t ohz (5) t olz t aa t rc t oh t aa d out address t oh
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 6 ? ac electrical characteristics (t a = -40 o c to +85 o c) write cycle cycle time : 55ns (v cc = 4.5~5.5v) cycle time : 70ns (v cc = 3.0~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t wc write cycle time 55 -- -- 70 -- -- ns t av w h t aw address valid to end of write 55 -- -- 70 -- -- ns t e1lwh t cw chip select to end of write 55 -- -- 70 -- -- ns t wlwh t wp write pulse width 35 -- -- 40 -- -- ns t av w l t as address set up time 0 -- -- 0 -- -- ns t whax t wr write recovery time (ce, we) 0 -- -- 0 -- -- ns t wlqz t whz write to output high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 35 -- -- 40 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whqx t ow end of write to output active 5 -- -- 5 -- -- ns ? switching waveforms (write cycle) write cycle 1 (1) t wc t wr (3) t cw (11) t wp (2) t aw t ohz (4 , 10) t as t dh t dw d in d out we ce oe address (5)
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 7 write cycle 2 (1,6) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is def ined by the overlap of ce and we low. all signals must be active to initiate a write and any one si gnal can terminate a writ e by going inactive. the data input setup and hold timing should be refe renced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. t wc t cw (11) t wp (2) t aw t whz (4 , 10) t as t dh t dw d in d out we ce t ow (7) (8) (8 , 9) address ( 5 )
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 8 ? ordering information note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described he rein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be exp ected to result in significant injury or death, including life- support systems and critical medical instruments. ? package dimensions sop - 28 0.020 0.005x45 package d: dice s: sop t: tsop (8mm x 13.4mm) p: pdip bs62lv256 x x z y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material g: green, rohs compliant p: pb free, rohs compliant
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 9 ? package dimensions (continued) 1 14 14 d 1 hd c l 28 15 "a" 15 28 0.004 ~ 0.006 0.004 ~ 0.008 0.0045 0.0026 0.0315 0.004 0.0197 0.022 0.004 0.008 0.001 0 ~ 8 0.004 max. 0.528 0.008 0.315 0.004 0.465 0.004 0.009 0.002 0.039 0.002 0.0433 0.004 inch c1 l1 0 y d e hd l e symbol c a a 1 b a 2 b1 unit 0.10 ~ 0.16 0.80 0.10 0 ~ 8 0.1 max. 0.55 0.10 11.80 0.10 0.50 13.40 0.20 8.00 0.10 - 0.004 +0.008 - 0.10 +0.20 0.115 0.065 mm 0.10 ~ 0.21 0.20 0.03 0.22 0.05 1.00 0.05 1.10 0.10 tsop - 28 with plating section a-a base metal c c1 b1 b (2x) e b 12 (2x) e gauge plane l1 l a a 0 0.254 y 12 (2x) 12 (2x) pdip - 28
bs62 l v 256 r0201-bs62lv256 revision 2.7 oct. 2008 10 ? revision history revision no. history draft date remark 2.4 add icc1 characteristic parameter jan. 13, 2006 2.5 change i-grade operation temperature range may. 25, 2006 - from ?25 o c to ?40 o c 2.6 revised i ccsb1 sepc. sep. 05, 2006 - from 1.0ua to 4.0ua for 5v c-grade - from 2.0ua to 5.0ua for 5v i-grade - from 0.2ua to 0.4ua for 3v c-grade - from 0.4ua to 0.7ua for 3v i-grade revised i ccdr sepc. - from 0.2ua to 0.4ua for c-grade - from 0.4ua to 0.7ua for i-grade 2.7 revised i ccdr sepc. oct. 31, 2008 - from 0.7ua to 0.4ua for i-grade - from 0.4ua to 0.3ua for c-grade typical value of standby current is replaced by maximum value in featues and description section remove ?-: normal? (leaded) pkg material in ordering information
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